1. Field of the Invention
The present invention relates generally to a stack structure of circuit boards embedded with semiconductor chips, and more particularly to a multi-layer circuit board structure which is formed by stacking a plurality of circuit boards having been embedded with semiconductor chips.
2. Description of Related Art
In order to meet increasing demands for lighter and smaller electronic products, semiconductor chips having different functionality are needed to be embedded in a circuit board in high density. Generally, two or more semiconductor chips are stack mounted to a chip carrier such as a substrate or a lead frame and electrically conductive to the chip carrier by solder wires.
FIG. 1 shows a multi-chip semiconductor package 1 of U.S. Pat. No. 5,323,060. A first semiconductor chip 12a is mounted on a circuit board 11 and electrically conductive to the circuit board 11 by first solder wires 13a. A second semiconductor chip 12b is stack mounted on the first semiconductor chip 12a through an adhesive layer 14. The adhesive layer 14 can be made of epoxy or tape. Thereafter, the second semiconductor chip 12b is electrically conductive to the circuit board 11 by second solder wires 13b. However, the wire bonding process of the first semiconductor chip 12a should be finished before stacking the second semiconductor chip 12b, that is, the die bonding process and wire bonding process should be separately performed for each stacked semiconductor chip, which accordingly complicates the fabrication process of the semiconductor package. Further, to efficiently prevent the second semiconductor chip 12b from contacting the first solder wires 13a, the thickness of the adhesive layer 14 should be bigger than the height of the wire arc of the first solder wires 13a. As a result, the thickness of the multi-chip semiconductor package 1 is increased, thereby limiting the fabrication of much lighter and smaller electronic products. Meanwhile, because it is difficult to evenly control the thickness of the adhesive layer 14, the second semiconductor chip 12b or the second solder wires 13b are easy to be contacted with the first solder wires 13a and accordingly the problems such as short circuits may be generated.
Also, with the integration trend of electronic products, to improve functionality of electronic products and decrease height of the electronic products, semiconductor chips are generally embedded in carrier boards. The embedded semiconductor chips can be active components or passive components. As shown in FIG. 2, a carrier board 20 having at least one opening 200 is provided, and a semiconductor chip 21 is mounted in the opening 200. The semiconductor chip 21 has an active surface 21a having a plurality of electrode pads 212. A dielectric layer 22 is formed on the carrier board 20 and the active surface 21a of the semiconductor chip 21. A circuit layer 23 is formed on the dielectric layer 22. The circuit layer 23 has a plurality of conductive structures 231 for electrically conductive to the electrode pads 212 of the semiconductor chip 21. Using a circuit build-up process, multi-layer circuit layers and dielectric layers can be formed so as to form a multi-layer circuit board.
To improve electrical performance of the carrier board 20, the number of the semiconductor chips 21 accordingly should be increased. Therefore, a plurality of openings 200 have to be formed in the carrier board 20. However, the limited size of the carrier board 20 limits the number of the openings and thus limits the improvement of the electrical performance of the carrier board 20.
Therefore, there is a need to provide a structure of circuit boards embedded with semiconductor chips that can overcome the above drawbacks.